Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
3937
26.11
SIO I
2
C 2 Memory Mapped I/O Registers
Table 264.
Summary of I
2
C 2 Memory Mapped I/O Registers—BAR 
Offset
Size 
(Bytes)
Register Name (Register Symbol)
Default 
Value
0–3h
4
0000007Fh
4–7h
4
00001055h
8–Bh
4
00000055h
C–Fh
4
00000001h
10–13h
4
00000000h
14–17h
4
00000190h
18–1Bh
4
000001D6h
1C–1Fh
4
“Fast Speed I2C Clock SCL High Count Register (IC_FS_SCL_HCNT)—Offset 
0000003Ch
20–23h
4
00000082h
24–27h
4
0000000Ch
28–2Bh
4
00000020h
2C–2Fh
4
00000000h
30–33h
4
000008FFh
34–37h
4
00000000h
38–3Bh
4
“I2C Receive FIFO Threshold Register (IC_RX_TL)—Offset 38h” on page 3950
00000010h
3C–3Fh
4
00000010h
40–43h
4
00000000h
44–47h
4
00000000h
48–4Bh
4
“Clear RX_OVER Interrupt Register (IC_CLR_RX_OVER)—Offset 48h” on 
00000000h
4C–4Fh
4
00000000h
50–53h
4
00000000h
54–57h
4
00000000h
58–5Bh
4
00000000h
5C–5Fh
4
“Clear ACTIVITY Interrupt Register (IC_CLR_ACTIVITY)—Offset 5Ch” on 
00000000h
60–63h
4
00000000h