Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4188
Datasheet
27.6.1
Receive Buffer Register/Transmit Holding Register/Divisor
Latch (Low). (RBR_THR_DLL)—Offset 0h
Register is used for different purposes depending on the mode. See description details
Access Method
Default: 00000000h
74–77h
4
00000000h
78–7Bh
4
00000000h
7C–7Fh
4
00000006h
80–83h
4
00000000h
84–87h
4
00000000h
88–8Bh
4
00000000h
8C–8Fh
4
00000000h
90–93h
4
00000000h
94–97h
4
00000000h
98–9Bh
4
00000000h
9C–9Fh
4
00000000h
A0–A3h
4
00000000h
A4–A7h
4
00000000h
A8–ABh
4
00000000h
F4–F7h
4
00043F32h
F8–FBh
4
3330382Ah
FC–FFh
4
44570110h
800–803h
4
00000000h
804–807h
4
00000000h
808–80Bh
4
00000050h
818–81Bh
4
00000000h
820–823h
4
00000000h
Table 278.
Summary of HSUART 1 Memory Mapped I/O Registers—BAR (Continued)
Offset
Size
(Bytes)
Register Name (Register Symbol)
Default
Value
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:30, F:3] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
0
rbr
_
thr_d
ll