Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4280
Datasheet
28.7.3
Revision ID and Class Code (REVCLASSCODE)—Offset 8h
Access Method
Default: 00000000h
28.7.4
Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch
Access Method
Default: 00800000h
1
0h
RW
Memory Space Enable (MSE):
This bit controls Bridge's response to downstream
Memory accesses. When set, accesses to memory space of the device is enabled.
0
0h
RO
Reserved6:
Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CLAS
S
_
CO
D
E
S
RID
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
000000h
RO
Class Code (CLASS_CODES):
The Class Code register is read-only and used to
identify the generic function of the device and, in some cases, a specific register level
programming interface. The register is broken into three byte size fields. The upper byte
(at offset 0Bh) is a base class code which broadly classifies the type of function the
device performs. The middle byte (at offset 0Ah) is a sub-class code which identifies
more specifically the function of the device. The lower byte (at offset 09h) identifies a
specific register-level programming interface (if any) so that device independent
software can interact with the device. This register is tied to a strap at the top level.
7:0
00h
RO
Revision ID (RID):
Revision ID identifies the revision of particular AHB device. This is
tied to a strap at the top level.
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Re
se
rv
ed
0
MU
LF
N
D
E
V
HE
A
D
E
R
TY
PE
LA
TT
IMER
CA
CHE
LINE
_
SIZE