Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – Power Management Controller (PMC)
Intel
®
Atom™ Processor E3800 Product Family
4310
Datasheet
30.2.6
Platform Clock Support
The SoC supports up to 6 clocks (PMC_PLT_CLK[5:0])with a frequency of either 19.2
MHz or 25 MHz. These clocks are available for general system use, where appropriate
and each have Control & Frequency register fields associated with them.
MHz or 25 MHz. These clocks are available for general system use, where appropriate
and each have Control & Frequency register fields associated with them.
Note:
Intel recommends 25 MHz. 19.2 MHz is not validated.
30.2.7
INIT# (Initialization) Generation
The INIT# functionality is implemented as a ‘virtual wire’ internal to the SoC rather
than a discrete signal. This virtual wire is asserted based on any one of the events
described in below table. When any of these events occur, INIT# is asserted for 16 PCI
clocks and then driven high.
than a discrete signal. This virtual wire is asserted based on any one of the events
described in below table. When any of these events occur, INIT# is asserted for 16 PCI
clocks and then driven high.
INIT#, when asserted, resets integer registers inside the CPU cores without affecting
its internal caches or floating-point registers. The cores then begin execution at the
power on Reset vector configured during power on configuration.
its internal caches or floating-point registers. The cores then begin execution at the
power on Reset vector configured during power on configuration.
30.3
USB Per-Port Register Write Control
The PMC contains the UPRWC.USB_PER_PORT_WE (USB Per-Port Registers Write
Enable) bit. When this bit is written from 0b to 1b, the UPRWC.WE_STS (Write Enable
Status) bit is asserted. This transaction initiates sync-SMI if the UPRWC.WE_SMIEN
(Write Enable SMI Enable) bit and the SMI_EN.USB_IS_SMI_EN (USB Intel Specific SMI
Enable) bit are set to 1b.
Enable) bit. When this bit is written from 0b to 1b, the UPRWC.WE_STS (Write Enable
Status) bit is asserted. This transaction initiates sync-SMI if the UPRWC.WE_SMIEN
(Write Enable SMI Enable) bit and the SMI_EN.USB_IS_SMI_EN (USB Intel Specific SMI
Enable) bit are set to 1b.
30.4
References
Advanced Configuration and Power Interface Specification, Revision 3.0:
http://
www.acpi.info/
30.5
Register Map
§
Table 292. INIT# Assertion Causes
Cause
Comment
PORT92.INIT_NOW transitions
from 0b to1b.
from 0b to1b.
RST_CNT.SYS_RST = 0b and
RST_CNT.RST_CPU transitions
from 0b to 1b
RST_CNT.RST_CPU transitions
from 0b to 1b