Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4414
Datasheet
31.5.46
TCGC (Trunk_Clock_Gating_Control_bios)—Offset 100h
Trunk_Clock_Gating_Control
Access Method
Default: 00000510h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SPI_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
SPI_BASE_ADDRESS Reference:
SPI_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 54h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0
RSVD
0
RSVD
FC
GDIS
SBCG
CD
EF
SB
CG
EN
S
B
CGC
N
T
Bit
Range
Default &
Access
Description
31:12
0b
RO
RSVD0:
Reserved
11
0b
RO
Reserved (RSVD):
Reserved.
10
1b
RW
FCGDIS:
Functional clock gating disable, chicken bit for the func_clk_gating FSM
9
0b
RW
SBCGCDEF:
SideBanb Control Gating Clock Defeature .Clock gate defeature bit which
allows the ISM to transition to idle, but prevents the final clock masking from occurring.
The value of this bit goes to the 'cgctrl_clkgatedef' port of the SideBand EndPoint
8
1b
RW
SBCGEN:
SideBanb Control Gating Clock Enable. Clock gate enable which prevents ISM
from leaving ACTIVE. Also prevents the clocks from being gated. The value of this bit
goes to the 'cgctrl_clkgaten' port of the SideBand EndPoint
7:0
10h
RW
SBCGCNT:
SideBanb Control Gating Clock Counter. Idle count limit for ISM which is
used to determine the block is idle.Recommended value 8'd16 . The value of those bits
goes to the 'cgctrl_idlecnt' ports of the SideBand EndPoint