Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

4423

The LCR, line control register is used at initialisation to set the communication 

parameters. Parity and number of data bits can be changed for example. The register 

also controls the accessibility of the DLL and DLM registers. These registers are 

mapped to the same I/O port as the RBR, THR and IER registers. Because they are only 

accessed at initialisation when no communication occurs this register swapping has no 

influence on performance.

Default: 00h

3:0

0001b

RO

 from this field indicates the highest priority pending 

interrupt which can be one of the following types: '0000' - modem status '0001' - no 

interrupt pending '0010' - THR empty '0100' - received data available '0110' - receiver 

line status '0111' - busy detect '1100' - character timeout Write to this field is split to 

four bits: Bit Description 3   DMA Mode, determines the DMA signalling mode used: '0'- 

mode 0, '1' - mode 1 2   XMIT FIFO Reset, resets the control portion of the transmit 

FIFO and treats the FIFO as empty. 1   RCVR FIFO Reset, resets the control portion of 

the receive FIFO and treats the FIFO as empty. 0   FIFO Enable. This enables/disables 

the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is 

changed both the XMIT and RCVR controller portion of FIFOs is reset.

I/O Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

0

DLAB

BC

SP

EP

S

PE

N

ST

O

P

DLS

7

0b

RW

This field is used to enable reading and writing of 

the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must 

be cleared after initial baud rate setup in order to access other registers. '0' - RBR, THR 

and IER accessible '1' - DLL and DLM accessible See Rx_Tx_Buffer and IER registers 

description for more details.

6

0b

RW

This is used to cause a break condition to be transmitted to the 

receiving device. If set to one the serial output is forced to the spacing (logic 0) state. 

When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until 

the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the 

sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is 

internally looped back to the receiver and the sir_out_n line is forced low.

5

0b

RO

Reserved and read as zero

4

0b

RW

This is used to select between even and odd parity, when 

parity is enabled (PEN set to one). If set to one, an even number of logic 1s is 

transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or 

checked.

3

0b

RW

This is used to enable and disable parity generation and 

detection in transmitted and received serial character respectively. '0' - parity disabled 

'1' - parity enabled