Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4528

Datasheet

This register is a combination of two registers the Revision ID register and the Class 

Code register. The revision ID register specifies a device specific revision identifier. The 

value is chosen by the vendor. Zero is an acceptable value. The Class Code register is 

read-only and is used to identify the generic function of the device and, in some cases, 

a specific registerlevel programming interface.

Default: 06010000h

14

0b

RW

This bit must be set whenever the device asserts 

SERR#. Set when the LPC bridge signals a system error to the internal SERR# logic.

13

0b

RW

This bit must be set by a master device whenever its 

transaction (except for Special Cycle) is terminated with Master-Abort. All master 

devices must implement this bit.

12

0b

RW

This bit must be set by a master device whenever its 

transaction is terminated with Target-Abort. All master devices must implement this bit.

11

0b

RW

This bit must be set by a target device whenever it 

terminates a transaction with Target-Abort. Devices that will never signal Target- Abort 

do not need to implement this bit.

10:9

01b

RO

These bits encode the timing of DEVSEL#. These are 

encoded as 00b for fast, 01b for medium, and 10b for slow (11b is reserved). These bits 

Indicate medium timing, although this has no meaning on the backbone

8

0b

RW

This bit is only implemented by bus masters. It is 

set when three conditions are met: 1) the bus agent asserted PERR# itself (on a read) 

or observed PERR# asserted (on a write); 2) the agent setting the bit acted as the bus 

master for the operation in which the error occurred; and 3) the Parity Error Response 

bit (Command register) is set.

7

0b

RO

This optional read-only bit indicates whether or 

not the target is capable of accepting fast back-to-back transactions when the 

transactions are not to the same agent. This bit can be set to 1 if the device can accept 

these transactions and must be set to 0 otherwise. This bit has no meaning on internal 

backbone.

6

0b

RO

Reserved

5

0b

RO

This optional read-only bit indicates whether or not this device 

is capable of running at 66 MHz. A value of zero indicates 33 MHz. A value of 1 indicates 

that the device is 66 MHz capable. This bit has no meaning on internal backbone

4

1b

RO

This optional read-only bit indicates whether or not this 

device implements the pointer for a New Capabilities linked list at offset 34h. A value of 

zero indicates that no New Capabilities linked list is available. A value of one indicates 

that the value read at offset 34h is a pointer in Configuration Space to a linked list of 

new capabilities. There is a capabilities list in the LPC bridge.

3

0b

RO

This read-only bit reflects the state of the interrupt in the 

device/function. Only when the Interrupt Disable bit in the command register is a 0 and 

this Interrupt Status bit is a 1, will the device's/function's INTx# signal be asserted. 

Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. The LPC 

bridge does not generate interrupts

2:0

0b

RO

Reserved

PCI Configuration Register

(Size: 32 bits)