Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
PCU – iLB – 8254 Timers
Intel
®
Atom™ Processor E3800 Product Family
4552
Datasheet
37.2
Features
37.2.1
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is
programmed for Mode 3 operation. The counter produces a square wave with a period
equal to the product of the counter period (838 ns) and the initial count value. The
counter loads the initial count value one counter period after software writes the count
value to the counter I/O address. The counter initially asserts IRQ0 and decrements the
count value by two each counter period. The counter negates IRQ0 when the count
value reaches 0. It then reloads the initial count value and again decrements the initial
count value by two each counter period. The counter then asserts IRQ0 when the count
value reaches 0, reloads the initial count value, and repeats the cycle, alternately
asserting and negating IRQ0.
programmed for Mode 3 operation. The counter produces a square wave with a period
equal to the product of the counter period (838 ns) and the initial count value. The
counter loads the initial count value one counter period after software writes the count
value to the counter I/O address. The counter initially asserts IRQ0 and decrements the
count value by two each counter period. The counter negates IRQ0 when the count
value reaches 0. It then reloads the initial count value and again decrements the initial
count value by two each counter period. The counter then asserts IRQ0 when the count
value reaches 0, reloads the initial count value, and repeats the cycle, alternately
asserting and negating IRQ0.
37.2.2
Counter 1, Refresh Request Signal
This counter is programmed for Mode 2 operation and impacts the period of the
NSC.RTS register bit. Programming the counter to anything other than Mode 2 results
in undefined behavior.
NSC.RTS register bit. Programming the counter to anything other than Mode 2 results
in undefined behavior.
37.2.3
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a write to the NSC.SDE register bit.
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a write to the NSC.SDE register bit.
37.3
Use
37.3.1
Timer Programming
The counter/timers are programmed in the following fashion:
1. Write a control word to select a counter.
2. Write an initial count for that counter.
3. Load the least and/or most significant bytes (as required by Control Word Bits 5, 4)
of the 16-bit counter.
4. Repeat with other counters.
Only two conventions need to be observed when programming the counters. First, for
each counter, the control word must be written before the initial count is written.
Second, the initial count must follow the count format specified in the control word
(least significant byte only, most significant byte only, or least significant byte and then
most significant byte).
each counter, the control word must be written before the initial count is written.
Second, the initial count must follow the count format specified in the control word
(least significant byte only, most significant byte only, or least significant byte and then
most significant byte).