Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
5056
Datasheet
39.9.12
Sus Trigger Negative Edge Enable 2
(cfio_ioreg_SUS_TNE_43_32_)—Offset 30h
Access via PCU Proxy, the register trigger Negative Edge Enable: When set to a 1, the
corresponding GPIO signal (if enabled in the GPIO_USE_SEL register) will case an GPE
or SMI when a 1 to 0 transition occurs. When set to 0, the GPIO signal is not enabled to
trigger an GPE or SMI on a 1 to 0 transition. - Only the 8 lsb are used in VLV
Access Method
Default: 00000000h
Type:
I/O Register
(Size: 32 bits)
GBASE Type:
PCI Configuration Register (Size: 32 bits)
GBASE Reference:
[B:0, D:31, F:0] + 48h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
res
er
ved
2
tne
Bit
Range
Default &
Access
Field Name (ID): Description
31:12
0h
RO
Reserved (reserved2):
Reserved.
11:0
0h
RW
Tne (tne):
bit 11 - USB_ULPI_0_REFCLK
bit 10 - USB_ULPI_0_STP
bit 9 - USB_ULPI_0_NXT
bit 8 - USB_ULPI_0_DIR
bit 7 - USB_ULPI_0_DATA7
bit 6 - USB_ULPI_0_DATA6
bit 5 - USB_ULPI_0_DATA5
bit 4 - USB_ULPI_0_DATA4
bit 3 - USB_ULPI_0_DATA3
bit 2 - USB_ULPI_0_DATA2
bit 1 - USB_ULPI_0_DATA1
bit 0 - USB_ULPI_0_DATA0