Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

5061

128–12Bh

4

“Sec Gpio Sus10 Pad Value (cfio_regs_pad_sec_gpio_sus10_PAD_VAL)—Offset

128h” on page 5135

00000002h

130–133h

4

“Sus Stat B Pad Configuration (cfio_regs_pad_sus_stat_b_PCONF0)—Offset

130h” on page 5136

2003CD00h

138–13Bh

4

“Sus Stat B Pad Value (cfio_regs_pad_sus_stat_b_PAD_VAL)—Offset 138h” on

00000002h

13C–13Fh

4

“Sus Stat B Pad Test (cfio_regs_pad_sus_stat_b_PAD_DFT)—Offset 13Ch” on

00000400h

140–143h

4

“Pmu Slp S0ix B Pad Configuration (cfio_regs_pad_pmu_slp_s0ix_b_PCONF0)—

Offset 140h” on page 5140

2003CD00h

148–14Bh

4

“Pmu Slp S0ix B Pad Value (cfio_regs_pad_pmu_slp_s0ix_b_PAD_VAL)—Offset

148h” on page 5143

00000002h

14C–14Fh

4

“Pmu Slp S0ix B Pad Test (cfio_regs_pad_pmu_slp_s0ix_b_PAD_DFT)—Offset

14Ch” on page 5143

00000400h

150–153h

4

“Gpio Dfx5 Pad Configuration (cfio_regs_pad_gpio_dfx5_PCONF0)—Offset

150h” on page 5144

2003CC80h

158–15Bh

4

“Gpio Dfx5 Pad Value (cfio_regs_pad_gpio_dfx5_PAD_VAL)—Offset 158h” on

00000002h

160–163h

4

“Gpio Dfx4 Pad Configuration (cfio_regs_pad_gpio_dfx4_PCONF0)—Offset

160h” on page 5148

2003CD00h

168–16Bh

4

“Gpio Dfx4 Pad Value (cfio_regs_pad_gpio_dfx4_PAD_VAL)—Offset 168h” on

00000002h

170–173h

4

“Gpio Dfx0 Pad Configuration (cfio_regs_pad_gpio_dfx0_PCONF0)—Offset

170h” on page 5151

2003CD00h

178–17Bh

4

“Gpio Dfx0 Pad Value (cfio_regs_pad_gpio_dfx0_PAD_VAL)—Offset 178h” on

00000002h

180–183h

4

“Gpio Dfx6 Pad Configuration (cfio_regs_pad_gpio_dfx6_PCONF0)—Offset

180h” on page 5154

2003CC80h

188–18Bh

4

“Gpio Dfx6 Pad Value (cfio_regs_pad_gpio_dfx6_PAD_VAL)—Offset 188h” on

00000002h

190–193h

4

“Gpio Dfx7 Pad Configuration (cfio_regs_pad_gpio_dfx7_PCONF0)—Offset

190h” on page 5158

2003CC80h

198–19Bh

4

“Gpio Dfx7 Pad Value (cfio_regs_pad_gpio_dfx7_PAD_VAL)—Offset 198h” on

00000002h

1A0–1A3h

4

“Gpio Dfx8 Pad Configuration (cfio_regs_pad_gpio_dfx8_PCONF0)—Offset

1A0h” on page 5161

2003CC80h

1A8–1ABh

4

“Gpio Dfx8 Pad Value (cfio_regs_pad_gpio_dfx8_PAD_VAL)—Offset 1A8h” on

00000002h

1B0–1B3h

4

“Gpio Dfx3 Pad Configuration (cfio_regs_pad_gpio_dfx3_PCONF0)—Offset

1B0h” on page 5164

2003CD00h

1B8–1BBh

4

“Gpio Dfx3 Pad Value (cfio_regs_pad_gpio_dfx3_PAD_VAL)—Offset 1B8h” on

00000002h

1C0–1C3h

4

“Gpio Dfx2 Pad Configuration (cfio_regs_pad_gpio_dfx2_PCONF0)—Offset

1C0h” on page 5167

2003CD00h

1C8–1CBh

4

“Gpio Dfx2 Pad Value (cfio_regs_pad_gpio_dfx2_PAD_VAL)—Offset 1C8h” on

00000002h

1D0–1D3h

4

“Gpio Sus0 Pad Configuration (cfio_regs_pad_gpio_sus0_PCONF0)—Offset

1D0h” on page 5171

2003CC80h

Table 340.

Summary of iLB GPIO S5 Memory Mapped I/O Registers—IOBASE + 0x2000

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value