Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
914
Datasheet
15
0b
RW
COLOR_CORRECTION_MATRIX_ENABLE_ON_PIPE_B:
1 = Color Correction
Coefficients are enabled to perform color correction
0 = Color Correction Coefficients are disabled
14
0b
RW
DISPLAYPORT_POWER_MODE_SWITCH_DEVVLVP:
This bit selects the software
controlled progressive to progressive power saving mode (software controlled DRRS).
Hardware Controlled Refresh Rate Select must be disabled when enabling this. Link and
data M/N 1 values are used for normal settings, M/N 2 values are used for low power
settings.
0 Normal progressive refresh rate (default)
1 Low Power progressive refresh rate
13
0b
RW
COLOR_RANGE_SELECT:
[DevVLVP]: This bit is used to select the color range of RBG
outputs.
0 = Apply full 0-255 color range to the output (Default)
1 = Apply 16-235 color range to the output
12
0b
RW
S3D_SPRITE_ORDER:
This bit controls the blending order of the sprite planes for S3D
support:
0 = Sprite C first. The first line or pixel comes from Sprite C (default)
1 = Sprite D first. The first line or pixel comes from Sprite D
11:10
0b
RW
S3D_SPRITE_INTERLEAVING_FORMAT:
These bits control the Sprite C/D
interleaving format in S3D mode
00 = No interleaving
01 = Line interleaving
10 = Pixel interleaving
11 = Reserved
9:8
0b
RW
RESERVED_1:
[DevCDV, DevVLVP] MBZ
Scrambling enable [DevCTG]: This bit enables scrambling for DisplayPort. Software
must set this bit appropriately when enabling a DisplayPort output.
00 = Scrambling disabled (Default)
01 = Scrambling enabled, no SR after initialization at loop 2 of training
10 - RESERVED
11 = Scrambling and SR enabled. Scrambling is reset every 512 BS symbols.
7:5
0b
RW
BITS_PER_COLOR:
[DevCTG, DevCDV, DevVLVP]: This field selects the number of bits
per color sent to a receiver device connected to this port. Color format takes place on
the Vblank after being written. Color format change can be done independent of a pixel
clock change.
Selecting a pixel color depth higher or lower than the pixel color depth of the frame
buffer results in dithering the output stream.
For further details on Display Port fixed frequency programming to accommodate these
formats refer to DP Frequency Programming in DPLL section of Bspec.
000 = 8 bits per color (Default)
001 = 10 bits per color
010 = 6 bits per color
011 = RESERVED
1xx = RESERVED
4
0b
RW
DITHERING_ENABLE:
[DevCTG, DevCDV]: This bit enables dithering for DisplayPort
6bpc or 8bpc modes
0 Dithering disabled (Default)
1 Dithering enabled
Programming Note: Dithering should only be enabled for 8bpc or 6bpc.
3:2
0b
RW
DITHERING_TYPE:
[DevCTG, DevCDV]: This bit selects dithering type for DisplayPort
6bpc or 8bpc modes
00 - Spatial only (default)
01- Spatio-Temporal 1
10- Spatio-Temporal 2 (testmode)
11- Temporal only (testmode)
1
0b
RW
DDA_RESET_TEST_MODE:
[DevCTG, DevCDV]:
0 Do not reset DDA
1 Reset DDA every 8th display frame
0
0b
RW
RESERVED_2:
Write as zero
Bit
Range
Default &
Access
Field Name (ID): Description