Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2347
29
0b
RWC
Received Master-Abort Status (RMA_0):
This bit is set when USB2, as a master,
receives a master-abort status on a memory access. This is treated as a Host Error and
halts the DMA engines. This event can optionally generate an SERR# by setting the
SERR# Enable bit and the SERR on Aborts Enable (bit 3, offset 84h). Software clears
this bit by writing a '1' to this bit location.
Power Well:
Core
28
0b
RWC
Received Target Abort Status (RTA_0):
This bit is set when USB2, as a master,
receives a target abort status on a memory access. This is treated as a Host Error and
halts the DMA engines. This event can optionally generate an SERR# by setting the
SERR# Enable bit and the SERR on Aborts Enable (bit 3, offset 84h). Software clears
this bit by writing a '1' to this bit location.
Power Well:
Core
27
0b
RO
Signaled Target-Abort Status (STA_0):
This bit is used to indicate when the USB2
function responds to a cycle with a target abort. There is no reason for this to happen,
so this bit will be hard-wired to '0'. Read-Only
Power Well:
Core
26:25
01b
RO
DEVSEL# Timing Status (DEVT_0):
This 2-bit field defines the timing for DEVSEL#
assertion. Read-Only.
Power Well:
Core
24
0b
RWC
Master Data Parity Error Detected (MDPED_0):
This bit is set whenever a data
parity error is detected on a USB2 read completion packet on the internal interface to
the USB2 host controller and bit 6 of the Command register is set to 1. Software clears
this bit by writing a '1' to this bit location.
Power Well:
Core
23
1b
RO
Fast Back-to-Back Capable (FBCAP_0):
Reserved as '1'.
Power Well:
Core
22
0b
RO
User Definable Features (UDF_0):
Reserved as '0'
Power Well:
Core
21
0b
RO
66 Mhz Capable (CLKCAP_0):
Reserved as '0'
Power Well:
Core
20
1b
RO
Capabilities List (CAPLIST_0):
Hardwired to '1' indicating that offset 34h contains a
valid capabilities pointer.
Power Well:
Core
19
0b
RO
Interrupt Status (INTRSTS_0):
This read-only bit reflects the state of this function's
interrupt at the input of the enable/disable logic. This bit is a 1 when the interrupt is
asserted. This bit will be 0 when the interrupt is deasserted. The value reported in this
bit is independent of the value in the Interrupt Enable bit.
Power Well:
Core
18:11
00000000b
RO
Reserved (RSVD):
Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description