Intel N2820 FH8065301616603 Data Sheet

Datasheet

1095

Trunk_Clock_Gating_Control

Default: 00000510h

§ §

0

0b

RW

Write Protect Disable (WPD): When set, access to the BIOS space is enabled for both 

read and write cycles. When cleared, only read cycles are permitted to the flash. When 

LE bit is set this bit could be written from a 1'b0 to a 1'b1 only by SMM code. When not 

SMM code tries to writes this bit from a 1'b0 to a 1'b1, bit remain in its 1'b0 value. An 

Async-SMI is generated (Send ASSERT_SMI) if SMIWPEN is set. This ensures that only 

SMM code can update BIOS.

Type: Memory Mapped I/O Register

(Size: 32 bits)

SPI_BASE_ADDRESS Type: PCI Configuration Register (Size: 32 

bits)
SPI_BASE_ADDRESS Reference: [B:0, D:31, F:0] + 54h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0

RSV

D

0

RSVD

FC

GDIS

SBCG

CD

EF

SBC

G

E

N

S

B

CGCN

T

31:12

0b

RO

RSVD0: Reserved

11

0b

RO

Reserved (RSVD): Reserved.

10

1b

RW

FCGDIS: Functional clock gating disable, chicken bit for the func_clk_gating FSM

9

0b

RW

SBCGCDEF: SideBanb Control Gating Clock Defeature .Clock gate defeature bit which 

allows the ISM to transition to idle, but prevents the final clock masking from occurring. 

The value of this bit goes to the 'cgctrl_clkgatedef' port of the SideBand EndPoint

8

1b

RW

SBCGEN: SideBanb Control Gating Clock Enable. Clock gate enable which prevents ISM 

from leaving ACTIVE. Also prevents the clocks from being gated. The value of this bit 

goes to the 'cgctrl_clkgaten' port of the SideBand EndPoint

7:0

10h

RW

SBCGCNT: SideBanb Control Gating Clock Counter. Idle count limit for ISM which is 

used to determine the block is idle.Recommended value 8'd16 . The value of those bits 

goes to the 'cgctrl_idlecnt' ports of the SideBand EndPoint