Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
1211
PCU - iLB – Low Pin Count (LPC) Bridge
25.6.1
Identifiers Register (PCIE_REG_Identifiers)—Offset 0h
Access Method
Default: 00008086h
25.6.2
Command (PCIE_REG_COMMAND)—Offset 4h
The Command register provides coarse control over a device's ability to generate and
respond to PCI cycles. When a 0 is written to this register, the device is logically
disconnected from the PCI bus for all accesses except configuration accesses. All
devices are required to support this base level of functionality. Individual bits in the
Command register may or may not be implemented depending on a device's
functionality
Access Method
Default: 0007h
Type: PCI Configuration Register
(Size: 32 bits)
PCIE_REG_Identifiers: [B:0, D:31, F:0] + 0h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0
DID
VID
Bit
Range
Default &
Access
Description
31:16
X
RO
Device Identification (DID): This field identifies the particular device. This identifier
is allocated by the vendor. This field is controlled by the LPC DID fuses Bits [31:23] are
coming from the SETIDVALUE message Device ID[15:7] bits. Bits [22:21] are set
constantly to 2'b00. Bits [20:16] are set constantly by pcu_did fuses.
15:0
8086h
RO
Vendor Identification (VID): This field identifies the manufacturer of the device.
Valid vendor identifiers are allocated by the PCI SIG to ensure uniqueness. 0 FFFFh is an
invalid value for Vendor ID.
Type: PCI Configuration Register
(Size: 16 bits)
PCIE_REG_COMMAND: [B:0, D:31, F:0] + 4h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
RSV
D
0
ID
FBE
SEE
WC
C
PE
RE
VG
A_P
S
E
MW
IE
SC
E
BM
E
MSE
IOSE
Bit
Range
Default &
Access
Description
15:11
0b
RO
RSVD0: Reserved
10
0b
RO
Interrupt Disable (ID): This bit disables the device/function from asserting INTx#. A
value of 0 enables the assertion of its INTx# signal. A value of 1 disables the assertion
of its INTx# signal. The LPC bridge has no interrupts to disable
9
0b
RO
Fast Back to Back Enable (FBE): This optional read/write bit controls whether or not
a master can do fast back-to-back transactions to different devices. A value of 0 means
fast back-to-back transactions are only allowed to the same agent
8
0b
RW
SERR# Enable (SEE): This bit is an enable bit for the SERR# driver. A value of 0
disables the SERR# driver. A value of 1 enables the SERR# driver.