Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
PCU – iLB – High Precision Event Timer (HPET)
1252
Datasheet
28.1.2.2
Mapping Option #1: Legacy Option (GCFG.LRE set)
This forces the mapping indicated in the following table.
28.1.2.3
Mapping Option #2: Standard Option (GCFG.LRE cleared)
Each timer has its own routing control. The interrupts can be routed to various
interrupts in the I/O APIC. T[2:0]C.IRC indicates which interrupts are valid options for
routing. If a timer is set for edge-triggered mode, the timers should not be shared with
any other interrupts.
interrupts in the I/O APIC. T[2:0]C.IRC indicates which interrupts are valid options for
routing. If a timer is set for edge-triggered mode, the timers should not be shared with
any other interrupts.
28.2
References
28.3
Register Map
28.4
Memory Mapped Registers
The register space is memory mapped to a 1K block at address FED00000h. All
registers are in the core well. Accesses that cross register boundaries result in
undefined behavior.
registers are in the core well. Accesses that cross register boundaries result in
undefined behavior.
Table 190. 8254 Interrupt Mapping
Timer
8259 Mapping
APIC Mapping
Comment
0
IRQ0
IRQ2
The 8254 timer will not cause any interrupts
1
IRQ8
IRQ8
RTC will not cause any interrupts.
2
T2C.IR
T2C.IRC