Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
PCU – iLB – GPIO
1262
Datasheet
29
PCU – iLB – GPIO
There are 102 GPIOs available for use during the S0 ACPI state, and 44 are available
for use from S5 to S0 (SUS). Most of these GPIOs can be used as legacy GPIOs through
IO registers. This chapter describes their use as legacy GPIOs.
for use from S5 to S0 (SUS). Most of these GPIOs can be used as legacy GPIOs through
IO registers. This chapter describes their use as legacy GPIOs.
29.1
Signal Descriptions
See
for additional details.
The signal description table has the following headings:
•
Signal Name: The name of the signal/pin
•
Direction: The buffer direction can be either input, output, or I/O (bidirectional)
•
Type: The buffer type found in
•
Description: A brief explanation of the signal’s function
29.2
Features
GPIOs can generate general purpose events (GPEs) on rising and/or falling edges.
I
O
I
O
I
O
I
O
I
O
I
O
O
Platform Control Unit
UAR
T
LP
C
GP
IO
IO
RTC
HPE
T
82
5
5
9
APIC
82
5
5
4
iLB
SPI
PM
C
C
I
O
SMB
Table 192. GPIO Signals
Signal Name
Direction/
Type
Description
GPIO_S0_SC[101:0]
I/O
Varies
These GPIO pins are powered and active in S0 only. Many of
these are multiplexed with other functions and may have
different default pin names.
GPIO_S5[43:0]
I/O
Varies
These GPIO pins are powered and active in S5–S0 (SUS). Many
of these are multiplexed with other functions and may have
different default pin names. Some are used as straps.