Intel N2820 FH8065301616603 Data Sheet

268

Datasheet

Default: 0001C020h

Type: Message Bus Register

(Size: 32 bits)

Op Codes:
0h - Read, 1h - Write

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0

re

se

rv

ed

528

re

se

rv

ed

527

cri_lane

re

se

t_clkg

atec

tl

cri_lane

reqforce

cr

i_su

sclkdisable

_de

la

y_4_0

cr

i_data_dy

n

clkgate

_

mode

_1_0

cr

i_eios_w

aittime_o

vren

cr

i_e

ios

_w

aittime

_6_0

31:24

0h

RW

reserved528: reserved

23:17

0h

RW

reserved527: reserved

16

1h

RW

cri_lanereset_clkgatectl: 1: The assertion of lane reset will have the effect of gating 

the susclk and de-asserting the internal laneclkreq. This mode is only valid when the 

data lane dynamic clock gating mode is set to a non-zero value (that is, 01, 10, and 

11). 0: The assertion of lane reset will have no effect on the gating of susclk and state 

of the internal laneclkreq signal.

15

1h

RW

cri_lanereqforce: Controls whether the internal laneclkreq will be forced to 1 or 0 

when cfg_data_dynclkgate_mode is set to 00 or 10. 1: force laneclkreq high 0: force 

laneclkreq low. This mode will likely be used when one of the lanes is disabled while 

other lanes in the family are enabled. In this case the internal laneclkreq of the disabled 

lane should be de-asserted (not influencing the clk gating decision)

14:10

10h

RW

cri_susclkdisable_delay_4_0: This register will control the number of cycles to delay 

the susclk enable de-assertion, in addition to the de-assertion of the laneclkreq signal 

sent out of the datalane. The susclk enable must be continuously de-asserted for the 

duration of this delay in order for the de-asserted state to be captured by the clock 

gating controller. 5'b00000 - 0 Cycle Delay 5'b00001 - 1 Cycle Delay 5'b00010 - 2 Cycle 

Delay ................ 5'b11110 - 30 Cycle Delay 5'b11111 - 31 Cycle Delay