Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
USB Host Controller Interfaces (xHCI, EHCI)
346
Datasheet
14.6.2
Device ID (DID)—Offset 2h
Access Method
Default: 8C31h
14.6.3
Command (CMD)—Offset 4h
Access Method
Default: 0000h
Type: PCI Configuration Register
(Size: 16 bits)
Power Well: Core
15
12
8
4
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
DID
Bit
Range
Default &
Access
Description
15:0
8C31h
RO/V
Device ID (DID): See Global Device ID table in Chap. 6 for value
Type: PCI Configuration Register
(Size: 16 bits)
Power Well: Core
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
SVD
ID
FBE
SERR
WCC
PE
R
VP
S
MW
I
SC
E
BME
MSE
IOSE
Bit
Range
Default &
Access
Description
15:11
00h
RO
Reserved (RSVD): Reserved.
10
0b
RW
Interrupt Disable (ID): When cleared to 0, the function is capable of generating
interrupts. When 1, the function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit is not affected by the interrupt enable.
9
0b
RO
Fast Back to Back Enable (FBE): Reserved.
8
0b
RW
SERR# Enable (SERR): When set to 1, the XHC is capable of generating (internally)
SERR#. See section on error handling.
7
0b
RO
Wait Cycle Control (WCC): Reserved.
6
0b
RW
Parity Error Response (PER): When set to 1, the XHCI Host Controller will check for
correct parity (on its internal interface) and halt operation when bad parity is detected
during the data phase as recommended by the XHCI specification. Note that this applies
to both requests and completions from the system interface. This bit must be set in
order for the parity errors to generate SERR#.
5
0b
RO
VGA Palette Snoop (VPS): Reserved.