Intel N2820 FH8065301616603 Data Sheet

376

Datasheet

The RW/L property of this register is controlled by the ACCTRL bit.

Default: 00000000h

Type: PCI Configuration Register

(Size: 32 bits)

Power Well: Core

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Rsvd

1

USB3SSENM

31:4

0000000h

RO

Rsvd1: Reserved.

3:0

0h

RW/L

USB3 SS Enable Mask (USB3SSENM): This field allows the BIOS to communicate to 

the OS which USB 3.0 ports can have the SuperSpeed capabilities enabled. When set to 

1, The OS may enable or disable the SuperSpeed capabilities by modifying the 

corresponding USB3SSEN bit. When set to 0, The OS shall not modify the corresponding 

USB3SSEN bit. BIOS shall set this bit to a '1' if the corresponding USB3SSEN bit is RW, 

unless the BIOS has cleared the USB2HCSELM bit for a USB 2.0 port and the BIOS 

wishes the OS to disable the corresponding SuperSpeed terminations for that physical 

connector. Port to bit mapping is in one-hot encoding; that is, bit 0 controls port 1 and 

so on.