Intel N2820 FH8065301616603 Data Sheet

Datasheet

47

Most message bus registers are located in the Processor Transaction Router. The default 
opcode messages for those registers are as follows:

•

Message ‘Read Register’ Opcode: 06h

•

Message ‘Write Register’ Opcode: 07h

Registers with different opcodes will be specified as applicable. Pseudo code of a 
message bus register read is shown below (where ReadOp==0x06):

•

MyMCR[31:24] = ReadOp; MyMCR[23:16] = port; MyMCR[15:8] = offset;

•

MyMCR[7:4] = 0xf

•

PCIWRITE(0, 0, 0, 0xD0, MyMCR)

•

Register_Snapshot = PCIREAD(0, 0, 0, 0xD4)

OpCode (typically 10h for read, 11h for write)

31:24

Port

23:16

Offset/Register

15:08

Byte Enable

07:04

Offset/Register Extension. This is used for messages sent to end points that require more 

than 8 bits for the offset/register. These bits are a direct extension of MCR[15:8].

31:08

RO

Read Only

In some cases, if a register is read only, writes to this register location have no effect. 

However, in other cases, two separate registers are located at the same location 

where a read accesses one of the registers and a write accesses the other register. 

See the I/O and memory map tables for details.

WO

Write Only

In some cases, if a register is write only, reads to this register location have no effect. 

However, in other cases, two separate registers are located at the same location 

where a read accesses one of the registers and a write accesses the other register. 

See the I/O and memory map tables for details.

R/W

Read/Write

A register with this attribute can be read and written. 

R/WC

Read/Write Clear

A register bit with this attribute can be read and written. However, a write of 1 clears 

(sets to 0) the corresponding bit and a write of 0 has no effect.