Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Power Management
66
Datasheet
•
Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency:
— If the target frequency is higher than the current frequency, core_VCC_S3is
voltage is optimized based on the selected frequency:
— If the target frequency is higher than the current frequency, core_VCC_S3is
ramped up slowly to an optimized voltage. This voltage is signaled by the SVID
signals to the voltage regulator. Once the voltage is established, the PLL locks
on to the target frequency.
signals to the voltage regulator. Once the voltage is established, the PLL locks
on to the target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the SVID signals.
voltage on the SVID signals.
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The processor controls voltage ramp rates by requesting appropriate ramp rates
from an external SVID controller.
from an external SVID controller.
•
Because there is low transition latency between P-states, a significant number of
transitions per second are possible.
transitions per second are possible.
•
Thermal Monitor mode.
— Please refer to Thermal Management Chapter
— Please refer to Thermal Management Chapter
6.3.2
Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following condition:
number of L2 cache ways upon each Deeper Sleep entry under the following condition:
•
The C0 timer that tracks continuous residency in the Normal state, has not expired.
This timer is cleared during the first entry into Deeper Sleep to allow consecutive
Deeper Sleep entries to shrink the L2 cache as needed.
This timer is cleared during the first entry into Deeper Sleep to allow consecutive
Deeper Sleep entries to shrink the L2 cache as needed.
•
The predefined L2 shrink threshold is triggered.
The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in
the BBL_CR_CTL3 MSR. The C0 timer is referenced through the
CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2
cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the
ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing
decisions.
the BBL_CR_CTL3 MSR. The C0 timer is referenced through the
CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2
cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the
ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing
decisions.
6.3.3
Low-Power Idle States
When the processor core is idle, low-power idle states (C-states) are used to save
power. More power savings actions are taken for numerically higher C-state. However,
higher C-states have longer exit and entry latencies. Resolution of C-state occur at the
thread, processor core, and processor core level.
power. More power savings actions are taken for numerically higher C-state. However,
higher C-states have longer exit and entry latencies. Resolution of C-state occur at the
thread, processor core, and processor core level.
6.3.3.1
Clock Control and Low-Power States
The processor core supports low power states at core level. The central power
management logic ensures the entire processor core enters the new common processor
core power state. For processor core power states higher than C1, this would be done
management logic ensures the entire processor core enters the new common processor
core power state. For processor core power states higher than C1, this would be done