Intel N2820 FH8065301616603 Data Sheet

Datasheet

775

11

0h

RW

reg_rcvdetect_pulse_width_ovrd: override enable for rcvdetect_pulse_width

10:8

0h

RW

reg_rcvdetect_pulse_width_2_0: override value for rcvdetect_pusle_width

7

1h

RW

reg_tx1_soft_reset_n: Active low reset to independently reset Tx lane1 in Display 

Port 0: Lane 1 reset 1: Lane 1 active

6

0h

RW

reg_tx_8b10b_bypass: Bypass 8b10b encoder ( for SAPIS etc interface.) 0 = Disable 

8b/10b encoder bypass 1 = Enable 8b/10b encoder bypass

5

0h

RW

reg_tx_laneup: Unused in Tx

4

0h

RW

reg_left_txfifo_rst_master2: override enable = reg_lanedeskew_strap_ovrd

3

0h

RW

reg_right_txfifo_rst_master2: override enable = reg_lanedeskew_strap_ovrd

2

0h

RW

reg_plllinksynch_ovrden: Override enable for reg_plllinsync_ovrd 0 = Use default 

delay in hardware 1 = Use reg_plllinksynch_ovrd

1

0h

RW

reg_plllinksynch_ovrd: override value for plllinksynch

0

0h

RW

reg_tx1_cmmdisparity: Sets the initial disparity during Compliance Measurement 

Mode, used together with pcs_txcompliance pulse. 0 = set negative disparity 1 = set 

positive disparity