Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
987
PCU – Power Management Controller (PMC)
NOTES:
1.
Most of the status bits (except otherwise is noted) are set according to event occurrence regardless to the enable bit.
2.
GPIO status bits are set only if enable criteria is true. GPIO_ROUT[n]=10b & GPE0a_EN.x_GPIO_EN[n] for
GPE0a_STS.x_GPIO_STS[n] (SCI). GPIO_ROUT[n]=01b & ALT_GPIO_SMI. x_GPIO_SMI_EN[n]=1b for
ALT_GPIO_SMI.x_GPIO_SMI_STS[n] (SMI).
3.
When power button override occurs, the system will transition immediately to S5. The SCI will only occur after the next
wake to S0 if the residual status bit (PM1_STS_EN.PWRBTNOR_STS) is not cleared prior to setting PM1_CNT.SCI_EN.
4.
PM1_STS_EN.GBL_STS being set will cause an SCI, even if the PM1_CNT.SCI_EN bit is not set. Software must take great
care not to set the SMI_ENBIOS_RLS bit (which causes PM1_STS_EN.GBL_STS to be set) if the SCI handler is not in place.
5.
No enable bits for these SCI/SMI messages in the PMC. Enable capability should be implemented in the source unit.
6.
Sync SMI has the same message opcode toward T-Unit. Special treatment regarding this Sync SMI is holding completion
to host till SYNC_SMI_ACK message is received from T-Unit.
7.
Sync SMI has the same message opcode toward T-Unit. Special treatment regarding this Sync SMI is holding the
SSMI_ACK message to iLB till SYNC_SMI_ACK message is received from T-Unit.
8.
The G-Unit is an internal functional sub-block which forms part of the graphics functional block.
9.
The GPE0a_STS.CORE_GPIO_STS[31:24] & GPE0a_EN.CORE_GPIO_EN[31:24] register bits correspond to
GPIO_S0_SC[7:0]. GPE0a_STS.SUS_GPIO_STS[23:16] & GPE0a_EN.SUS_GPIO_EN[23:16] correspond to GPIO_S5[7:0].
10.
The ALT_GPIO_SMI.CORE_GPIO_SMI_STS[31:24] & ALT_GPIO_SMI.CORE_GPIO_SMI_EN[15:8] register bits correspond
to GPIO_S0_SC[7:0]. ALT_GPIO_SMI.SUS_GPIO_SMI_STS[23:16] & ALT_GPIO_SMI.SUS_GPIO_SMI_EN[7:0] correspond
to GPIO_S5[7:0].
20.2.6
Platform Clock Support
The processor supports up to 6 clocks (PMC_PLT_CLK[5:0]) with a frequency of either
19.2 MHz or 25 MHz. These clocks are available for general system use, where
appropriate and each have Control & Frequency register fields associated with them.
19.2 MHz or 25 MHz. These clocks are available for general system use, where
appropriate and each have Control & Frequency register fields associated with them.
Note:
Intel recommends 25 MHz. 19.2 MHz is not validated.
20.2.7
INIT# (Initialization) Generation
The INIT# functionality is implemented as a ‘virtual wire’ internal to the processor
rather than a discrete signal. This virtual wire is asserted based on any one of the
events described in below table. When any of these events occur, INIT# is asserted for
16 PCI clocks and then driven high.
rather than a discrete signal. This virtual wire is asserted based on any one of the
events described in below table. When any of these events occur, INIT# is asserted for
16 PCI clocks and then driven high.
INIT#, when asserted, resets integer registers inside the CPU cores without affecting
its internal caches or floating-point registers. The cores then begin execution at the
power on Reset vector configured during power on configuration.
its internal caches or floating-point registers. The cores then begin execution at the
power on Reset vector configured during power on configuration.
20.3
USB Per-Port Register Write Control
The PMC contains the UPRWC.USB_PER_PORT_WE (USB Per-Port Registers Write
Enable) bit. When this bit is written from 0b to 1b, the UPRWC.WE_STS (Write Enable
Status) bit is asserted. This transaction initiates sync-SMI if the UPRWC.WE_SMIEN
(Write Enable SMI Enable) bit and the SMI_EN.USB_IS_SMI_EN (USB Intel Specific SMI
Enable) bit are set to 1b.
Enable) bit. When this bit is written from 0b to 1b, the UPRWC.WE_STS (Write Enable
Status) bit is asserted. This transaction initiates sync-SMI if the UPRWC.WE_SMIEN
(Write Enable SMI Enable) bit and the SMI_EN.USB_IS_SMI_EN (USB Intel Specific SMI
Enable) bit are set to 1b.
Table 149. INIT# Assertion Causes
Cause
Comment
PORT92.INIT_NOW transitions
from 0b to1b.
RST_CNT.SYS_RST = 0b and
RST_CNT.RST_CPU transitions
from 0b to 1b