Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
1113
PCU – System Management Bus (SMBus)
Process Call
The process call is so named because a command sends data and waits for the slave to
return a value dependent on that data. The protocol is simply a Write Word followed by
a Read Word, but without a second command or stop condition.
return a value dependent on that data. The protocol is simply a Write Word followed by
a Read Word, but without a second command or stop condition.
When programmed for the Process Call command, the processor transmits the Transmit
Slave Address (SMB_Mem_TSA), Host Command (SMB_Mem_HCMD), Data 0
(SMB_Mem_HD0) and Data 1 (SMB_Mem_HD1) registers. Data received from the
device is stored in the Data 0 (SMB_Mem_HD0) and Data 1 (SMB_Mem_HD1)
registers. The Process Call command with SMB_Config_HCFG.I2C_EN set and the
SMB_Config_HCTL.PECEN bit set produces undefined results. Software must force
SMB_Config_HCTL.PECEN & SMB_Mem_AUXC.AAC to 0b when running this command.
See section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0
for the format of the protocol.
Slave Address (SMB_Mem_TSA), Host Command (SMB_Mem_HCMD), Data 0
(SMB_Mem_HD0) and Data 1 (SMB_Mem_HD1) registers. Data received from the
device is stored in the Data 0 (SMB_Mem_HD0) and Data 1 (SMB_Mem_HD1)
registers. The Process Call command with SMB_Config_HCFG.I2C_EN set and the
SMB_Config_HCTL.PECEN bit set produces undefined results. Software must force
SMB_Config_HCTL.PECEN & SMB_Mem_AUXC.AAC to 0b when running this command.
See section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0
for the format of the protocol.
Note:
For process call command, the value written into SMB_Mem_TSA.RW needs to be 0b.
Block Read/Write
The processor contains a 32-byte buffer for read and write data which can be enabled
by setting SMB_Mem_AUXC.E32B, as opposed to a single byte of buffering. This 32-
byte buffer is filled with write data before transmission, and filled with read data on
reception. In the processor, the interrupt is generated only after a transmission or
reception of 32 bytes, or when the entire byte count has been transmitted/received.
by setting SMB_Mem_AUXC.E32B, as opposed to a single byte of buffering. This 32-
byte buffer is filled with write data before transmission, and filled with read data on
reception. In the processor, the interrupt is generated only after a transmission or
reception of 32 bytes, or when the entire byte count has been transmitted/received.
The byte count field is transmitted but ignored by the processor as software will end
the transfer after all bytes it cares about have been sent or received.
the transfer after all bytes it cares about have been sent or received.
For a Block Write, software must either force both the SMB_Config_HCTL.PECEN and
SMB_Mem_AUXC.AAC bits to 0b when running this command.
SMB_Mem_AUXC.AAC bits to 0b when running this command.
The block write begins with a slave address and a write condition. After the command
code the processor issues a byte count describing how many more bytes will follow in
the message. If a slave had 20 bytes to send, the first byte would be the number 20
(14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or
Write is allowed to transfer a maximum of 32 data bytes.
code the processor issues a byte count describing how many more bytes will follow in
the message. If a slave had 20 bytes to send, the first byte would be the number 20
(14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or
Write is allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address
(SMB_Mem_TSA), Host Command (SMB_Mem_HCMD) and Data 0 (SMB_Mem_HD0)
registers are sent. Data is then sent from the Host Block Data (SMB_Mem_HBD)
register; the total data sent being the value stored in the Data 0 (SMB_Mem_HD0)
register. On block read commands, the first byte received is stored in the Data 0
(SMB_Mem_HD0) register, and the remaining bytes are stored in the Host Block Data
(SMB_Mem_HBD) register. See section 5.5.7 of the System Management Bus (SMBus)
Specification, Version 2.0 for the format of the protocol.
(SMB_Mem_TSA), Host Command (SMB_Mem_HCMD) and Data 0 (SMB_Mem_HD0)
registers are sent. Data is then sent from the Host Block Data (SMB_Mem_HBD)
register; the total data sent being the value stored in the Data 0 (SMB_Mem_HD0)
register. On block read commands, the first byte received is stored in the Data 0
(SMB_Mem_HD0) register, and the remaining bytes are stored in the Host Block Data
(SMB_Mem_HBD) register. See section 5.5.7 of the System Management Bus (SMBus)
Specification, Version 2.0 for the format of the protocol.
Note:
The processor will still send the number of bytes (on writes) or receive the number of
bytes (on reads) indicated in the Data 0 (SMB_Mem_HD0) register. However, it will not
send the contents of the Data 0 (SMB_Mem_HD0) register as part of the message.
bytes (on reads) indicated in the Data 0 (SMB_Mem_HD0) register. However, it will not
send the contents of the Data 0 (SMB_Mem_HD0) register as part of the message.