Motorola Espresso Maker MC68340 User Manual

8- 4

MOTOROLA

Each timer provides seven interrupt request outputs (

IRQ7

–

IRQ1

) to notify the CPU32

that an interrupt has occurred. The interrupts are described in 8.4 Register Description.
Bits in the SR indicate all currently active interrupt conditions. The interrupt enable (IE)
bits in the control register (CR) are programmable to mask any events that may cause an
interrupt.

This section contains a brief description of the timer module signals (see Figure 8-3).

The terms 

assertion and negation are used throughout this

section to avoid confusion when dealing with a mixture of
active-low and active-high signals. The term 

assert or assertion

indicates that a signal is active or true independent of the level
represented by a high or low voltage. The term 

negate or

negation indicates that a signal is inactive or false.

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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