Motorola Espresso Maker MC68340 User Manual
MOTOROLA
MC68340 USER’S MANUAL
3- 3
Table 3-1. SIZx Signal Encoding
SIZ1
SIZ0
Transfer Size
0
1
Byte
1
0
Word
1
1
Three Bytes
0
0
Long Word
3.1.2 Function Code Signals
FC3–FC0 are outputs that indicate one of 16 address spaces to which the address
applies. Fifteen of these spaces are designated as either user or supervisor, program or
data, and normal or direct memory access (DMA) spaces. One other address space is
designated as CPU space to allow the CPU32 to acquire specific control information not
normally associated with read or write bus cycles. FC3–FC0 are valid while
applies. Fifteen of these spaces are designated as either user or supervisor, program or
data, and normal or direct memory access (DMA) spaces. One other address space is
designated as CPU space to allow the CPU32 to acquire specific control information not
normally associated with read or write bus cycles. FC3–FC0 are valid while
AS
is
asserted.
Function codes (see Table 3-2) can be considered as extensions of the 32-bit address
that can provide up to 16 different 4-Gbyte address spaces. Function codes are
automatically generated by the CPU32 to select address spaces for data and program at
both user and supervisor privilege levels, a CPU address space for processor functions,
and an alternate master address space. User programs access only their own program
and data areas to increase protection of system integrity and can be restricted from
accessing other information. The S-bit in the CPU32 status register is set for supervisor
accesses and cleared for user accesses to provide differentiation. Refer to 3.4 CPU
Space Cycles for more information.
that can provide up to 16 different 4-Gbyte address spaces. Function codes are
automatically generated by the CPU32 to select address spaces for data and program at
both user and supervisor privilege levels, a CPU address space for processor functions,
and an alternate master address space. User programs access only their own program
and data areas to increase protection of system integrity and can be restricted from
accessing other information. The S-bit in the CPU32 status register is set for supervisor
accesses and cleared for user accesses to provide differentiation. Refer to 3.4 CPU
Space Cycles for more information.
Table 3-2. Address Space Encoding
Function Code Bits
3
2
1
0
Address Spaces
0
0
0
0
Reserved (Motorola)
0
0
0
1
User Data Space
0
0
1
0
User Program Space
0
0
1
1
Reserved (User )
0
1
0
0
Reserved (Motorola)
0
1
0
1
Supervisor Data Space
0
1
1
0
Supervisor Program Space
0
1
1
1
CPU Space
1
x
x
x
DMA Space
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..