Motorola Espresso Maker MC68340 User Manual

3- 36

MOTOROLA

 

S0

S2

S4

S0

S2

S4

INTERNAL

PROCESSING

STACK
WRITE

WRITE

CYCLE

CLKOUT

DSACKx

R/W

AS

DS

BERR

FC3–FC0

D15–D0

A31–A0

≈

When both 

BERR

 and 

HALT

 are asserted by an external device during a bus cycle, the

MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is
similar to the delayed 

BERR

 signal described previously, can also occur (see Figure 3-20).

The MC68340 terminates the bus cycle, places the control signals in their inactive state,
and does not begin another bus cycle until the 

BERR

 and 

HALT

 signals are negated by

external logic. After a synchronization delay, the MC68340 retries the previous cycle using
the same access information (address, function code, size, etc.). 

BERR

 should be negated

before S2 of the retried cycle to ensure correct operation of the retried cycle.

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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