Fujitsu MB15F74UL Data Sheet
MB15F74UL
9
(2) Data setting
•
Binary 14
-
bit Programmable Reference Counter Data Setting
Note : Divide ratio less than 3 is prohibited.
•
Binary 11
-
bit Programmable Counter Data Setting
Note : Divide ratio less than 3 is prohibited
•
Binary 7
-
bit Swallow Counter Data Setting
Divide ratio
R14 R13 R12 R11 R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
•
•
•
16383
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Divide ratio N11 N10 N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
•
•
•
2047
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Divide ratio
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
•
•
•
127
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
• Programmable Counter
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
N1 to N11
: Divide ratio setting bits for the programmable counter (3 to 2,047)
LDS
: LD/fout signal select bit
SW
IF
/
RF
: Divide ratio setting bit for the prescaler (IF : SW
IF
, RF : SW
RF
)
FC
IF
/
RF
: Phase control bit for the phase detector (IF : FC
IF
, RF : FC
RF
)
CN1, 2
: Control bit
Note : Data input with MSB first.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
22
23
CN1 CN2 LDS
SW
IF
/
RF
FC
IF
/
RF
A1 A2 A3 A4 A5 A6 A7
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
(LSB)
(MSB)
Data Flow