Kingston Technology 2GB, 800MHz, DDR2, Non-ECC, CL5 (5-5-5-15), DIMM (Kit of 2) Tall HS, HyperX KHX6400D2T1K2/2G Data Sheet
Product codes
KHX6400D2T1K2/2G
Memory Module Specification
Document No. 4805095-001.A00
11/05/08
KHX6400D2T1K2/2G
2GB (1GB 128M x 64-Bit x 2 pcs.)
PC2-6400 CL5 240-Pin DIMM Kit
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T E C H N O L O G Y
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DESCRIPTION:
Kingston's KHX6400D2T1K2/2G is a kit of two 128M x 64-bit 1GB (1024MB) DDR2-800 CL5
SDRAM (Synchronous DRAM) memory modules, based on sixteen 64M x 8-bit DDR2 FBGA
components per module. Total kit capacity is 2GB (2048MB). Each module pair has been tested to run
at DDR2 800MHz at low latency timing of 5-5-5-15 at 2.0V. The SPD is programmed to JEDEC
standard latency 667Mhz timing of 5-5-5-15 at 1.8V. Each 240-pin DIMM uses gold contact fingers
and requires +1.8V. The electrical and mechanical specifications are as follows:
SDRAM (Synchronous DRAM) memory modules, based on sixteen 64M x 8-bit DDR2 FBGA
components per module. Total kit capacity is 2GB (2048MB). Each module pair has been tested to run
at DDR2 800MHz at low latency timing of 5-5-5-15 at 2.0V. The SPD is programmed to JEDEC
standard latency 667Mhz timing of 5-5-5-15 at 1.8V. Each 240-pin DIMM uses gold contact fingers
and requires +1.8V. The electrical and mechanical specifications are as follows:
FEATURES:
Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 5 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 5-5-5-15 at +1.8V / 5-5-5-15 at +2.0V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 5 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 5-5-5-15 at +1.8V / 5-5-5-15 at +2.0V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 2.401” (61.00mm) w/ heatsink, double sided component
PERFORMANCE:
Clock Cycle Time (tCK) CL=5
3ns (min.) / 8ns (max.)
Row Cycle Time (tRC)
54ns (min.)
Refresh to Active/Refresh Command Time (tRFC)
105ns
Row Active Time (tRAS)
39ns (min.) / 70,000ns (max.)
Single Power Supply of
+1.8V (+/- .1V)
Power
1.922 W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 55
o
C
Storage Temperature
-55
o
C to +125
o
C