Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2 User Manual

HYS[64/72]T512020EU–[25F/2.5/3S]–A

Unbuffered DDR2 SDRAM Modules

 Internet Data Sheet

Rev. 1.0, 2008-06

6

06112008-YHWK-B105

2

Pin Configurations and Block Diagrams

2.1

Pin Configurations

The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in 

 (240 pins). The abbreviations used

in columns Pin and Buffer Type are explained in 

 and 

 respectively. The pin numbering is depicted in 

for non-ECC modules (

×64) and 

 for ECC modules 

(×72).

185

CK0

I

SSTL

Clock Signals 2:0, Complement Clock Signals 2:0
The system clock inputs. All address and command lines are sampled on the 
cross point of the rising edge of CK and the falling edge of CK. A Delay 
Locked Loop (DLL) circuit is driven from the clock inputs and output timing for 
read operations is synchronized to the input clock.

137

CK1

I

SSTL

220

CK2

I

SSTL

186

CK0

I

SSTL

138

CK1

I

SSTL

221

CK2

I

SSTL

52

CKE0

I

SSTL

Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK 
signal when LOW. By deactivating the clocks, CKE LOW initiates the Power 
Down Mode or the Self Refresh Mode.

171

CKE1

I

SSTL

NC

NC

—

193

S0

I

SSTL

Chip Select Rank 1:0
Enables the associated DDR2 SDRAM command decoder when LOW and 
disables the command decoder when HIGH. When the command decoder is 
disabled, new commands are ignored but previous operations continue. Rank 
0 is selected by S0; Rank 1 is selected by S1. Ranks are also called "Physical 
banks".

76

S1

I

SSTL

NC

NC

—

192

RAS

I

SSTL

Row Address Strobe
When sampled at the cross point of the rising edge of CK,and falling edge of 
CK, RAS, CAS and WE define the operation to be executed by the SDRAM.

74

CAS

I

SSTL