Soyo SY-K7VTA User Manual



 Seamless DRAM command scheduling for maximum DRAM bus

utilization (e.g., precharge other banks while accessing the current

bank)

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 Four cache lines (32quadwords) of CPU to DRAM write buffers

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 Four cache lines 32 quadwords of CPU to DRAM read prefetch

buffers

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 Read around write capability for non-stalled CPU read

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 Burst read and write operation

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 BIOS shadow at 16KB increment

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 Decoupled and burst DRAM refresh with staggered RAS timing

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 CAS before RAS or self refresh