VXi VM4016 User Manual

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VM4016 Programming 

43 

 
The VM4016 can be operated upon using (a) Word Serial Commands or (b) Register Access. 
 
The VM4016 allows two types of register accesses (a) Direct Register Access using Hardware 
registers (b) Pseudo Register Access.  This can be configured using the INHOUSE:PSEUDO 
command. 
 
Direct Register Access is much faster than Pseudo Register Access.  However, the former does 
not provide certain features provided by the latter.  Using Pseudo Register Access (a) a register 
read of FIRST LATCHED data allow another FIRST LATCHED event to occur (b) allows for 
clearing of the first latched register upon register access rather than a Word Serial FETC:LATC? 
and (c) allows configuration of the type of backplane interrupting. 
 
The module can be enabled for backplane interrupts using the INHOUSE:REG_ENABLE 
command.  It can also be done by writing a non-zero value to the Interrupt Enable Register at 
offset 0x38 provided the module has been configured for Pseudo register access.  The module can 
be instructed to clear the first latched register on register access/WS read using the 
INHOUSE:CLEAR_LATCH command.  When VXIbus backplane interrupting is enabled, the 
module will generate interrupts whenever latching of the first latched register takes place.  If a 
Pseudo register access of the first latched register at offset 0x30 is performed or a Word Serial 
read (using FETC:LATC?) is performed, the latch register gets cleared allowing further latching 
to occur provided the module has been instructed to clear the first latched register.  If the clearing 
of the first latched register is disabled, after the first latching takes place, the module cannot 
generate backplane interrupts. 
 
Using the Direct Register Access, backplane interrupts are generated when the latching takes 
place for the first time.  For further interrupting to occur, the Word Serial FETC:LATC? query 
must be performed. 
 
Two types of backplane interrupts can be generated.  They are (a) the reqt/reqf (in response to an 
IACK cycle) or (b) a single backplane interrupt.  This can be configured using the 
INHOUSE:REGINT command.  However, it must be noted that the module can be configured 
for only for mode at any given point of time.  The former mode provides compatibility with the 
VXI standards and is the default mode.  The latter allows for faster processing since it cuts down 
servicing of interrupts by 50% (since only 1 interrupt needs to be serviced for each latch event).