Intel Core i7 Processor I7-940 AT80601000921AA User Manual

Datasheet 

91

While in C1/C1E state, the processor will process bus snoops and snoops from the 

other threads. 

Individual threads of the processor can enter the C3 state by initiating a P_LVL2 I/O 

read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, the processor 

flushes the contents of its caches. Except for the caches, the processor core maintains 

all its architectural state while in the C3 state. All of the clocks in the processor core are 

stopped in the C3 state.

Because the core’s caches are flushed, the processor keeps the core in the C3 state 

when the processor detects a snoop on the Intel QPI Link or when another logical 

processor in the same package accesses cacheable memory. The processor core will 

transition to the C0 state upon occurrence of an interrupt. RESET# will cause the 

processor core to initialize itself.

Individual threads of the processor can enter the C6 state by initiating a P_LVL3 read to 

the P_BLK or an MWAIT(C6) instruction. Before entering Core C6, the processor saves 

core state data (such as, registers) to the last level cache. This data is retired after 

exiting core C6. The processor achieves additional power savings in the core C6 state. 

The package supports C0, C3, and C6 power states. Note that there is no package C1 

state. The package power state is automatically resolved by the processor depending 

on the core power states and permission from the rest of the system as described in 

the following sections.

This is the normal operating state for the processor. The processor remains in the 

Normal state when at least one of its cores is in the C0 or C1 state or when another 

component in the system has not granted permission to the processor to go into a low 

power state. Individual components of the processor may be in low power states while 

the package in C0.

The package will enter the C1/C1E low power state when at least one core is in the 
C1/C1E state and the rest of the cores are in the C1/C1E or lower power state. The 
processor will also enter the C1/C1E state when all cores are in a power state lower 
than C1/C1E but the package low power state is limited to C1/C1E using the 
PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically 
transition to the lowest power operating point (lowest supported voltage and associated 
frequency). When entering the C1E state, the processor will first switch to the lowest 
bus ratio and then transition to the lower VID. No notification to the system occurs 
upon entry to C1/C1E.

The package will enter the C3 low power state when all cores are in the C3 or lower 

power state and the processor has been granted permission by the other component(s) 

in the system to enter the C3 state. The package will also enter the C3 state when all 

cores are in an idle state lower than C3 but other component(s) in the system have 

only granted permission to enter C3.