Samsung Microphone S3C84E5 User Manual
S3C84E5/C84E9/P84E9
INTERRUPT STRUCTURE
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INTERRUPT STRUCTURE
OVERVIEW
The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU
recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has
more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to
one or more sources.
recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has
more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to
one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can
issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible
interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an interrupt
request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to
device. The S3C84E5/C84E9/P84E9 interrupt structure recognizes eight interrupt levels.
issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible
interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an interrupt
request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to
device. The S3C84E5/C84E9/P84E9 interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is
determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR
settings lets you define more complex priority relationships between different levels.
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is
determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR
settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The
maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for
S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector
priorities are set in hardware. S3C84E5/C84E9/P84E9 uses twenty-one vectors.
maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for
S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector
priorities are set in hardware. S3C84E5/C84E9/P84E9 uses twenty-one vectors.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each
vector can have several interrupt sources. In the S3C84E5/C84E9/P84E9 interrupt structure, there are twenty-one
possible interrupt sources.
vector can have several interrupt sources. In the S3C84E5/C84E9/P84E9 interrupt structure, there are twenty-one
possible interrupt sources.
When a service routine starts, the respective pending bit should be either cleared automatically by hardware or
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method would be used to clear its respective pending bit.
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method would be used to clear its respective pending bit.