Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 100 of 760
5. On-Chip Peripheral Interrupts
— Conditions: The interrupt mask bits in SR are lower than the on-chip module (TMU, RTC,
SCI, IrDA, SCIF, A/D, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0. The
interrupt is accepted at an instruction boundary.
interrupt is accepted at an instruction boundary.
— Operations: The PC value after the instruction at which the interrupt is accepted is saved to
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to
the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC),
for more information.
the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC),
for more information.
6. UDI Interrupt
— Conditions: An UDI interrupt command is input (see section 22.4.4, UDI Interrupt),
SR.IMASK is lower than 15, and the BL bit in SR is 0. The interrupt is accepted at an
instruction boundary.
instruction boundary.
— Operations: The PC value after the instruction that accepts the interrupt is saved to SPC.
SR at the point the interrupt is accepted is saved to SSR. H'5E0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR +
H'0600. See section 6, Interrupt Controller (INTC), for more information.
INTEVT2. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR +
H'0600. See section 6, Interrupt Controller (INTC), for more information.
4.6
Cautions
•
Return from exception handling
Check the BL bit in SR with software. When SPC and SSR have been saved to external
memory, set the BL bit in SR to 1 before restoring them.
memory, set the BL bit in SR to 1 before restoring them.
Issue an RTE instruction, which sets SPC in PC and SSR in SR, and causes a branch to the
SPC address, and return from exception handling.
SPC address, and return from exception handling.
•
Operation when exception or interrupt occurs while SR.BL
=
1
Interrupt: Acceptance is suppressed until the BL bit in SR is cleared to 0. If there is an
interrupt request and the reception conditions are satisfied, the interrupt is accepted after
the execution of the instruction that clears the BL bit in SR to 0. In sleep or standby mode,
however, the interrupt will be accepted even when the BL bit in SR is 1.
interrupt request and the reception conditions are satisfied, the interrupt is accepted after
the execution of the instruction that clears the BL bit in SR to 0. In sleep or standby mode,
however, the interrupt will be accepted even when the BL bit in SR is 1.
Exception: No user break point trap will occur even when the break conditions are met.
When one of the other exceptions occurs, a branch is made to the fixed address of the reset
(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are
undefined. Differently from general reset processing, the
When one of the other exceptions occurs, a branch is made to the fixed address of the reset
(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are
undefined. Differently from general reset processing, the
RESETOUT pin is not asserted,
and reset status is output from the STATUS0 and STATUS1 pins.