Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 160 of 760
7.2.8
Break Bus Cycle Register B (BBRB)
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the
break conditions of channel B. A power-on reset initializes BBRB to H'0000.
or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the
break conditions of channel B. A power-on reset initializes BBRB to H'0000.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
CDB1
CDB0
IDB1
IDB0
RWB1
RWB0
SZB1
SZB0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 8—Reserved: These bits are always read as 0. These bits are always read as 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select B (CDB1, CDB0): Select the CPU cycle or
DMAC cycle as the bus cycle of the channel B break condition.
DMAC cycle as the bus cycle of the channel B break condition.
Bit 7: CDB1
Bit 6: CDB0
Description
0
0
Condition comparison is not performed
(Initial value)
*
1
The break condition is the CPU cycle
1
0
The break condition is the DMAC cycle
*
: Don’t care
Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1, IDB0): Select the instruction
fetch cycle or data access cycle as the bus cycle of the channel B break condition.
fetch cycle or data access cycle as the bus cycle of the channel B break condition.
Bit 5: IDB1
Bit 4: IDB0
Description
0
0
Condition comparison is not performed
(Initial value)
1
The break condition is the instruction fetch cycle
1
0
The break condition is the data access cycle
1
The break condition is the instruction fetch cycle or data access
cycle
cycle