Renesas Stereo System SH7709S User Manual

Rev. 5.00, 09/03, page 174 of 760

reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the
values in the queues are invalid. The read pointer stay at the position before PCTE is switched,
but the trace pointer restart at the bottom of the queues.

1. Register specifications

BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300400

Specified conditions: Channel A/channel B independent mode

•

Channel  A

Address:

H'00000404, Address mask: H'00000000

Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

No ASID check is included

•

Channel  B

Address:

H'00008010, Address mask: H'00000006

Data:

H'00000000, Data mask: H'00000000

Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

No ASID check is included

A user break occurs after an instruction of address H'00000404 is executed or before
instructions of adresses H'00008010 to H'00008016 are executed.