Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 214 of 760
9.6
Overview of WDT
9.6.1
Block Diagram of WDT
Figure 9.2 shows a block diagram of the WDT.
WTCSR
Standby
control
Bus interface
WTCNT
Divider
Clock selector
Clock
Standby
mode
mode
Peripheral
clock
clock
Standby
cancellation
Reset
control
Clock selection
WDT
Overflow
Internal
reset
request
Interrupt
control
Interrupt
request
WTCSR:
WTCNT:
Legend
Watchdog timer control/status register
Watchdog timer counter
Watchdog timer counter
Figure 9.2 Block Diagram of WDT
9.6.2
Register Configuration
The WDT has two registers that select the clock, switch the timer mode, and perform other
functions. Table 9.5 shows the WDT registers.
functions. Table 9.5 shows the WDT registers.
Table 9.5
Register Configuration
Name
Abbreviation
R/W
Initial Value
Address
Access Size
Watchdog timer counter
WTCNT
R/W
*
H'00
H'FFFFFF84
R: 8;
W: 16
W: 16
*
Watchdog timer
control/status register
control/status register
WTCSR
R/W
*
H'00
H'FFFFFF86
R: 8;
W: 16
W: 16
*
Note:
*
Write with word access. Write with H'5A and H'A5, respectively, in the upper byte. Byte or
longword writes are not possible. Read with byte access.
longword writes are not possible. Read with byte access.