Renesas Stereo System SH7709S User Manual

Rev. 5.00, 09/03, page 228 of 760

The BSC has 21 registers (table 10.2). Synchronous DRAM also has a built-in synchronous
DRAM mode register. These registers control direct connection interfaces to memory, wait states,
and refreshes devices.

*

Bus control register 1

BCR1

R/W

H'0000

H'FFFFFF60

16

Bus control register 2

BCR2

R/W

H'3FF0

H'FFFFFF62

16

Wait state control register 1

WCR1

R/W

H'3FF3

H'FFFFFF64

16

Wait state control register 2

WCR2

R/W

H'FFFF

H'FFFFFF66

16

Individual memory control
register

MCR

R/W

H'0000

H'FFFFFF68

16

PCMCIA control register

PCR

R/W

H'0000

H'FFFFFF6C

16

Refresh timer control/status
register

RTCSR

R/W

H'0000

H'FFFFFF6E

16

Refresh timer counter

RTCNT

R/W

H'0000

H'FFFFFF70

16

Refresh time constant register

RTCOR

R/W

H'0000

H'FFFFFF72

16

Refresh count register

RFCR

R/W

H'0000

H'FFFFFF74

16

Synchronous DRAM mode
register, area 2

SDMR

W

—

H'FFFFD000–
H'FFFFDFFF

8

Synchronous DRAM mode
register, area 3

H'FFFFE000–
H'FFFFEFFF

MCS0 control register

MCSCR0

R/W

H'0000

H'FFFFFF50

16

MCS1 control register

MCSCR1

R/W

H'0000

H'FFFFFF52

16

MCS2 control register

MCSCR2

R/W

H'0000

H'FFFFFF54

16

MCS3 control register

MCSCR3

R/W

H'0000

H'FFFFFF56

16

MCS4 control register

MCSCR4

R/W

H'0000

H'FFFFFF58

16

MCS5 control register

MCSCR5

R/W

H'0000

H'FFFFFF5A

16

MCS6 control register

MCSCR6

R/W

H'0000

H'FFFFFF5C

16

MCS7 control register

MCSCR7

R/W

H'0000

H'FFFFFF5E

16

Notes: For details, see section 10.2.7, Synchronous DRAM Mode Register (SDMR).

*

  Initialized by a power-on reset.