Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 381 of 760
CMCNT0 Count Timing
One of four clocks (P
φ
/4, P
φ
/8, P
φ
/16, P
φ
/64) obtained by dividing the P
φ
clock can be selected
with the CKS1 and CKS0 bits in CMCSR0. Figure 11.26 shows the timing.
N+1
CK
Internal clock
CMCNT0 input
clock
CMCNT0
N-1
N
Figure 11.26 Count Timing
11.4.4
Compare Match
Compare Match Flag Setting Timing
The CMF bit in the CMCSR0 register is set to 1 by the compare match signal generated when the
CMCOR0 register and the CMCNT0 counter match. The compare match signal is generated in the
final state of the match (timing at which the CMCNT0 counter matching count value is updated).
Consequently, after the CMCOR0 register and the CMCNT0 counter match, a compare match
signal will not be generated until a CMCNT0 counter input clock occurs. Figure 11.27 shows the
CMF bit setting timing.
CMCOR0 register and the CMCNT0 counter match. The compare match signal is generated in the
final state of the match (timing at which the CMCNT0 counter matching count value is updated).
Consequently, after the CMCOR0 register and the CMCNT0 counter match, a compare match
signal will not be generated until a CMCNT0 counter input clock occurs. Figure 11.27 shows the
CMF bit setting timing.