Renesas Stereo System SH7709S User Manual

Rev. 5.00, 09/03, page 428 of 760

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Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)

•

 

Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-
error interrupts are requested independently.

•

 

When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power.

Figure 14.1 shows a block diagram of the SCI.

RxD

TxD

SCK

SCI

SCBRR

SCSSR
SCSCR

SCTSR

SCRDR

SCRSR

SCSMR

SCPCR
SCPDR

Parity generation

Parity check

Clock

External clock

Module data bus

Internal
data bus

P

φ

P

φ

/4

P

φ

/16

P

φ

/64

TXI

TEI

RXI
ERI

Bus interface

Baud rate

generator

Transmit/

receive 

control

SCRSR:

SCRDR:

SCTSR:

SCTDR:

SCSMR:

Legend

Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register

SCSCR:

SCSSR:

SCBRR:
SCPDR:
SCPCR:

Serial control register
Serial status register
Bit rate register
SC port data register
SC port control register

SCTDR