Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 433 of 760
14.2.2
Receive Data Register (SCRDR)
The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of
one byte of serial data by moving the received data from the receive shift register (SCRSR) into
SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows
the SCI to receive data continuously.
one byte of serial data by moving the received data from the receive shift register (SCRSR) into
SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows
the SCI to receive data continuously.
The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby
or module standby mode.
or module standby mode.
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
14.2.3
Transmit Shift Register (SCTSR)
The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the
transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one-byte data, the SCI automatically loads the next transmit
data from SCTDR into SCTSR and starts transmitting again. If the TDRE bit in SCSSR is 1,
however, the SCI does not load the SCTDR contents into SCTSR. The CPU cannot read or write
to SCTSR directly.
transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one-byte data, the SCI automatically loads the next transmit
data from SCTDR into SCTSR and starts transmitting again. If the TDRE bit in SCSSR is 1,
however, the SCI does not load the SCTDR contents into SCTSR. The CPU cannot read or write
to SCTSR directly.
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—