Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 446 of 760
14.2.9
Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset, and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The SCBRR setting is calculated as follows:
Asynchronous mode: N
=
P
φ
64
×
2
2n – 1
×
B
×
10
6
– 1
Synchronous mode: N
=
P
φ
8
×
2
2n – 1
×
B
×
10
6
– 1
B:
Bit rate (bits/s)
N:
SCBRR setting for baud rate generator (0
≤
N
≤
255)
P
φ
: Operating frequency for peripheral modules (MHz)
n:
Baud rate generator clock source (n
=
0, 1, 2, 3) (for the clock sources and values of
n, see table 14.3.)
Table 14.3
SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
P
φ
0
0
1
P
φ
/4
0
1
2
P
φ
/16
1
0
3
P
φ
/64
1
1
Note:
The bit rate error in asynchronous is given by the following formula:
Error (
%
)
= (
P
φ ×
10
6
(N + 1)
×
B
×
64
×
2
2n – 1
) ×
100