Renesas Stereo System SH7709S User Manual

Rev. 5.00, 09/03, page 465 of 760

Figure 14.11 shows an example of SCI receive operation in asynchronous mode.

RDRF

FER

ERI interrupt
request generated
by framing error

1 frame

RXI interrupt handler 
reads data and clears 
RDRF bit to 0

RXI interrupt
request generated

0

1

1

1

0/1

0

1

Parity

bit

Parity

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle (mark)
state

D

0

D

1

D

7

D

0

D

1

D

7

0/1

The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).

In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which
it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting
processor sends transmit data with the multiprocessor bit cleared to 0.

Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.

Figure 14.12 shows an example of communication among processors using the multiprocessor
format.