Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 597 of 760
19.7
Port F
Port F is an 8-bit input port with the pin configuration shown in figure 19.6. Each pin has an input
pull-up MOS, which is controlled by the port F control register (PFCR) in the PFC.
pull-up MOS, which is controlled by the port F control register (PFCR) in the PFC.
PTF7 (input) / PINT15 (input) / TRST (input)
PTF6 (input) / PINT14 (input) / TMS (input)
PTF5 (input) / PINT13 (input) / TDI (input)
PTF4 (input) / PINT12 (input) / TCK (input)
PTF3 (input) / PINT11 (input) / IRLS3 (input)
PTF2 (input) / PINT10 (input) / IRSL2 (input)
PTF1 (input) / PINT9 (input) / IRLS1 (input)
PTF0 (input) / PINT8 (input) / IRLS0 (input)
PTF6 (input) / PINT14 (input) / TMS (input)
PTF5 (input) / PINT13 (input) / TDI (input)
PTF4 (input) / PINT12 (input) / TCK (input)
PTF3 (input) / PINT11 (input) / IRLS3 (input)
PTF2 (input) / PINT10 (input) / IRSL2 (input)
PTF1 (input) / PINT9 (input) / IRLS1 (input)
PTF0 (input) / PINT8 (input) / IRLS0 (input)
Port F
Figure 19.6 Port F
19.7.1
Register Description
Table 19.11 summarizes the port F register.
Table 19.11 Port F Register
Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port F data register
PFDR
R
H'
**
H'0400012A
(H'A400012A)
(H'A400012A)
*
1
8
Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either
access this register from the P2 area of logical space or else make an appropriate setting
using the MMU so that this register is not cached.
using the MMU so that this register is not cached.
*
Means no value.
*
1 When address translation by the MMU does not apply, the address in parentheses
should be used.