Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 606 of 760
19.11.2
Port K Data Register (PKDR)
Bit:
7
6
5
4
3
2
1
0
PK7DT
PK6DT
PK5DT
PK4DT
PK3DT
PK2DT
PK1DT
PK0DT
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The port K data register (PKDR) is an 8-bit readable/writable register that stores data for pins
PTK7 to PTK0. Bits PK7DT to PK0DT correspond to pins PTK7 to PTK0. When the pin function
is general output port, if the port is read, the value of the corresponding PKDR bit is returned
directly. When the function is general input port, if the port is read, the corresponding pin level is
read. Table 19.20 shows the function of PKDR.
PTK7 to PTK0. Bits PK7DT to PK0DT correspond to pins PTK7 to PTK0. When the pin function
is general output port, if the port is read, the value of the corresponding PKDR bit is returned
directly. When the function is general input port, if the port is read, the corresponding pin level is
read. Table 19.20 shows the function of PKDR.
PKDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
sleep mode, and in a manual reset.
Table 19.20 Port K Data Register (PKDR) Read/Write Operations
PKnMD1
PKnMD0
Pin State
Read
Write
0
0
Other function
(see table 18.1)
(see table 18.1)
PKDR value
Value is written to PKDR, but does not
affect pin state
affect pin state
1
Output
PKDR value
Write value is output from pin
1
0
Input (Pull-up
MOS on)
MOS on)
Pin state
Value is written to PKDR, but does not
affect pin state
affect pin state
1
Input (Pull-up
MOS off)
MOS off)
Pin state
Value is written to PKDR, but does not
affect pin state
affect pin state
(n = 0 to 7)