Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 630 of 760
Table 20.4
A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Symbol
Min
Typ
Max
Min
Typ
Max
A/D conversion start
delay
delay
t
D
17
—
28
10
—
17
Input sampling time
t
SPL
—
129
—
—
65
—
A/D conversion time
t
CONV
514
—
525
259
—
266
Note:
Values in the table are numbers of states (t
cyc
).
20.4.5
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE1 and TRGE0 bits are set to 1 in
ADCR, external trigger input is enabled at the
ADCR, external trigger input is enabled at the
ADTRG pin. A high-to-low transition at the
ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations,
regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software.
Figure 20.7 shows the timing.
regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software.
Figure 20.7 shows the timing.
A/D conversion
P
φ
ADTRG
External
trigger signal
ADST
Figure 20.7 External Trigger Input Timing