Renesas Stereo System SH7709S User Manual
Rev. 5.00, 09/03, page 673 of 760
23.3.3
AC Bus Timing
Table 23.7
Bus Timing
Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V,
Ta = –20 to 75°C
Ta = –20 to 75°C
Item
Symbol
Min
Max
Unit
Figure
Address delay time
t
AD
1.5
12
ns
23.16–23.36, 23.39–23.46
Address setup time
t
AS
0
—
ns
23.16–23.18
Address hold time
*
1
t
AH
4
—
ns
23.16–23.21
BS
delay time
t
BSD
—
10
ns
23.16–23.36, 23.40–23.46
CS
delay time 1
t
CSD1
0
10
ns
23.16–23.21, 23.40–23.46
CS
delay time 2
t
CSD2
—
10
ns
23.16–23.21
CS
delay time
(SDRAM access)
t
CSD3
1.5
10
ns
23.22–23.39
Read/write delay time
t
RWD
1.5
10
ns
23.16–23.46, 23.39–23.46
Read/write hold time
t
RWH
0
—
ns
23.16–23.21
Read strobe delay time
t
RSD
—
10
ns
23.16–23.21 23.40–23.43
Read data setup time 1
t
RDS1
6
—
ns
23.16–23.21, 23.40–23.46
Read data setup time 2
t
RDS2
5
—
ns
23.22–23.25, 23.30–23.33
Read data hold time 1
*
2
t
RDH1
0
—
ns
23.16–23.21, 23.40–23.46
Read data hold time 2
t
RDH2
1
—
ns
23.22–23.25, 23.30–23.33
Write enable delay time
t
WED
—
10
ns
23.16–23.18, 23.40, 23.41
Write data delay time 1
t
WDD1
—
14
ns
23.16–23.18, 23.40, 23.41, 23.44–23.46
Write data delay time 2
t
WDD2
1.5
12
ns
23.26–23.29, 23.34–23.36
Write data hold time 1
t
WDH1
1.5
—
ns
23.16–23.18, 23.40, 23.41, 23.44–23.46
Write data hold time 2
t
WDH2
1.5
—
ns
23.26–23.29, 23.34–23.36
Write data hold time 3
t
WDH3
2
—
ns
23.16–23.18
Write data hold time 4
t
WDH4
2
—
ns
23.40, 23.41, 23.44–23.46
WAIT
setup time
t
WTS
5
—
ns
23.17–23.21, 23.41, 23.43, 23.45, 23.46
WAIT
hold time
t
WTH
0
—
ns
23.17–23.21, 23.41, 23.43, 23.45, 23.46
RAS
delay time 2
t
RASD2
1.5
10
ns
23.22–23.39
CAS
delay time 2
t
CASD2
1.5
10
ns
23.22–23.39
DQM
delay time
t
DQMD
1.5
10
ns
23.22–23.36
CKE delay time
t
CKED
1.5
10
ns
23.38