Renesas M32R-FPU User Manual

3

3-70

M32R-FPU Software Manual (Rev.1.01)

DSP function instruction

Multiply and add

accumulator +=  (  ( signed ) ( Rsrc1 << 16 ) * ( signed short ) Rsrc2  ) ;

MACLO multiplies the low-order 16 bits of Rsrc1 and the low-order 16 bits of Rsrc2, then adds

the result to the low order 56 bits in the accumulator.

The LSB of the multiplication result is aligned with bit 47 in the accumulator, and the portion

corresponding to bits 8 through 15 of the accumulator is sign-extended before addition. The

result of the addition is stored in the accumulator.  The low-order 16 bits of Rsrc1 and Rsrc2 are

treated as signed values.

The condition bit (C) is unchanged.

None

Rsrc1

low-order 16 bits

Rsrc2

low-order 16 bits

x

0

15 16

31

0

+

0

15 16

31 32

47 48

63

7 8

Result of the multiplication

Value in accumulator before the
execution of the MACLO instruction

Value in accumulator after the
execution of the MACLO instruction

Sign extension

Sign extension

INSTRUCTIONS

3.2 Instruction description