Renesas M32R-FPU User Manual

3

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M32R-FPU Software Manual (Rev.1.01)

load/store instruction

Store

(1)  * ( signed short *) Rsrc2 = Rsrc1;

(2)  * ( signed short *) Rsrc2 = Rsrc1, Rsrc2 + = 2 ;

(3)  * ( signed short *) ( Rsrc2 + ( signed short ) disp16 ) = Rsrc1;

(1)  STH stores the least significant halfword of Rsrc1 in the memory at the address specified

by

       Rsrc2.

(2)  STH stores the LSB halfword of Rsrc1 to the memory of the address specified by Rsrc2,

and

       then increments Rsrc2 by 2.

(3)  STH stores the least significant halfword of Rsrc1 in the memory at the address specified

by

       Rsrc combined with the 16-bit displacement. The displacement  value is sign-ex-

tended to 32

       bits before the address calculation.

The condition bit (C) is unchanged.

Address exception (AE)

INSTRUCTIONS

3.2 Instruction description